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APW7120A
5V to 12V Supply Voltage, 8-PIN, Synchronous Buck PWM Controller
Features
* * *
Operating with Single 5~12V Supply Voltage or two Supply Voltages Drive Dual Low Cost N-Channel MOSFETs - Adaptive Shoot-Through Protection Built-in Feedback Compensation - Voltage-Mode PWM Control - 0~100% Duty Ratio - Fast Transient Response
General Description
The APW7120A is a fixed 300kHz frequency, voltage mode, and synchronous PWM controller. The device drives two low cost N-channel MOSFETs and is designed to work with single 5~12V or two supply voltage(s), providing excellent regulation for load transients. The APW7120A integrates controls, monitoring and protection functions into a single 8-pin package to provide a low cost and perfect power solution. A power-on-reset (POR) circuit monitors the VCC supply voltage to prevent wrong logic controls. An internal 0.8V reference provides low output voltage down to 0.8V for further applications. An built-in digital soft-start with fixed soft-start interval prevents the output voltage from overshoot as well as limiting the input current. The controller' over-current protection s monitors the output current by using the voltage drop across the low-side MOSFET' RDS(ON), eliminating the s need of a current sensing resistor. Additional under voltage and over voltage protections monitor the voltage on FB pin for short-circuit and over-voltage protections. The over-current protection cycles the soft-start function until 4 over-current events are counted. Pulling and holding the voltage on OCSET pin below 0.15V with an open drain device shuts down the controller.
*
2% 0.8V Reference - Over Line, Load Regulation, and Operating Temperature
* * * * *
Programmable Over-Current Protection - Using RDS(ON) of Low-Side MOSFET Hiccup-Mode Under-Voltage Protection 118% Over-Voltage Protection Adjustable Output Voltage Small Converter Size - 300kHz Constant Switching Frequency - Small SOP-8 Package
* * *
Built-In Digital Soft-Start Shutdown Control using an External MOSFET Lead Free and Green Devices Available (RoHS Compliant)
Applications
* * *
Motherboard Graphics Card High Current, up to 20A, DC-DC Converters
Pin Cinfiguration
BOOT 1 UGATE 2 GND 3 LGATE 4 8 PHASE 7 OCSET 6 FB 5 VCC
SOP-8
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Jun., 2008 1 www.anpec.com.tw
APW7120A
Ordering and Marking Information
APW7120A Package Code K : SOP-8 Operating Ambient Temperature Range E : -20 to 70 C Assembly Material Handling Code Handling Code TR : Tape & Reel Temperature Range Assembly Material Package Code L : Lead Free Device G : Halogen and Lead Free Device APW7120A XXXXX XXXXX - Date Code
APW7120A K :
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for MSL classification at lead-free peak reflow temperature. ANPEC defines "Green" to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight).
Absolute Maximum Ratings
Symbol VCC VBOOT Parameter VCC Supply Voltage (VCC to GND) BOOT Voltage (BOOT to PHASE) UGATE Voltage (UGATE to PHASE)
(Note 1)
Rating -0.3 ~ 16 -0.3 ~ 16 Unit V V V
<400ns pulse width >400ns pulse width LGATE Voltage (LGATE to GND) <400ns pulse width >400ns pulse width PHASE Voltage (PHASE to GND) <400ns pulse width >400ns pulse width VI/O Input Voltage (OCSET, FB to GND) Maximum Junction Temperature TSTG TSDR Storage Temperature Maximum Lead Soldering Temperature, 10 Seconds
-5 ~ VBOOT+0.3 -0.3 ~ VBOOT+0.3 -5 ~ VCC+0.3 -0.3 ~ VCC+0.3 -10 ~ 30 -3 ~ 16 -0.3 ~ 7 150 -65 ~ 150 260
V
V
V
o
C C
o o
C
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Thermal Characteristics
Symbol JA Parameter Junction-to-Ambient Resistance in Free Air
(Note 2)
Typical Value 160
Unit
o
C/W
Note 2: JA is measured with the component mounted on a high effective thermal conductivity test board in free air.
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APW7120A
Recommended Operating Conditions
Symbol VCC VOUT VIN IOUT TA TJ VCC Supply Voltage Converter Output Voltage Converter Input Voltage Converter Output Current Ambient Temperature Junction Temperature Parameter
(Note 3)
Range 4.5 ~ 13.2 0.8 ~ 80%VIN 2.2 ~ 13.2 0 ~ 20 -20 ~ 70 -20 ~ 125 Unit V V V A
o o
C
C
Note 3: Please refer to the typical application circuit.
Electrical Characteristics
Unless otherswise specified, these specifications apply over VCC = 12V, VBOOT = 12V and TA = -20 ~ 70oC. Typical values are at TA = 25oC.
APW7120A Symbol SUPPLY CURRENT IVCC VCC Nominal Supply Current VCC Shutdown Supply Current POWER-ON-RESET Rising VCC Threshold Hysteresis OSCILLATOR FOSC VOSC Free Running Frequency Ramp Amplitude 250 300 1.5 350 kHz VP-P 3.8 0.1 4.1 0.45 4.4 0.6 V V UGATE and LGATE Open 2.1 1.5 6 4 mA mA Parameter Test Conditions Min. Typ. Max. Unit
REFERENCE VOLTAGE VREF Reference Voltage Accuracy Line Regulation ERROR AMPLIFIER DC Gain FP1 FZ FP2 First Pole Frequency Zero Frequency Second Pole Frequency Average UGATE Duty Range FB Input Current 0 86 0.4 0.4 430 85 0.1 dB Hz kHz kHz % A Measured at FB Pin TA =-20~70C VCC=12 ~ 5V -2.0 0.8 0.05 +2.0 0.5 V % %
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APW7120A
Electrical Characteristics (Cont.)
Unless otherswise specified, these specifications apply over VCC = 12V, VBOOT = 12V and TA = -20 ~ 70oC. Typical values are at TA = 25oC.
APW7120A Symbol Parameter Test Conditions Min. Typ. Max. Unit
PWM CONTROLLER GATE DRIVERS UGATE Source UGATE Sink LGATE Source LGATE Sink TD Dead-Time VBOOT-PHASE =12V, VUGATE-PHASE =6V VBOOT-PHASE =12V, VUGATE-PHASE=1V VCC=12V, VLGATE=6V VCC=12V, VLGATE=1V Guaranteed by Design 1.0 1.0 2.0 3.5 1.9 2.6 40 7 5 100 A A ns
PROTECTIONS IOCSET OCSET Current Source Over-Current Reference Voltage UVFB FB Under-Voltage Threshold FB Under-Voltage Hysteresis Over-Voltage Threshold SOFT-START AND SHUTDOWN TSS Soft-Start Interval OCSET Shutdown Threshold OCSET Shutdown Hysteresis Falling VOCSET 2 0.1 3.8 0.15 40 5 0.3 ms V mV VPHASE=0V, Normal Operation TA =-20~70C VFB Falling Rising V VFB Rising 35 0.37 62 114 40 0.4 67 45 118 45 0.43 72 122 A V % mV %
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APW7120A
Function Pin Description
BOOT (Pin 1) This pin provides ground referenced bias voltage to the high-side MOSFET driver. A bootstrap circuit with a diode connected to 5~12V is used to create a voltage suitable to drive a logic-level N-channel MOSFET. UGATE (Pin 2) Connect this pin to the high-side N-channel MOSFET' s gate. This pin provides gate drive for the high-side MOSFET. GND (Pin 3) The GND terminal provides return path for the IC' bias s current and the low-side MOSFET driver' pull-low s current. Connect the pin to the system ground via very low impedance layout on PCBs. LGATE (Pin 4) Connect this pin to the low-side N-channel MOSFET' s gate. This pin provides gate drive for the low-side MOSFET. VCC (Pin 5) Connect this pin to a 5~12V supply voltage. This pin provides bias supply for the control circuitry and the low-side MOSFET driver. The voltage at this pin is monitored for the Power-On-Reset (POR) purpose. FB (Pin 6) This pin is the inverting input of the internal Gm amplifier. Connect this pin to the output (VOUT) of the converter via an external resistor divider for closed-loop operation. The output voltage set by the resistor divider is determined using the following formula :
V OUT = 0.8V ( 1 + R1 ) R2 (V)
where R1 is the resistor connected from VOUT to FB , and R2 is the resistor connected from FB to GND. The FB pin is also monitored for under and over-voltage events. OCSET (Pin 7) The OCSET is a dual-function input pin for overcurrent protection and shutdown control. Connect a resistor (ROCSET) from this pin to the Drain of the lowside MOSFET. This resistor, an internal 40A current source (IOCSET), and the MOSFET' on-resistance s (RDSON) set the converter over-current trip level (IPEAK) according to the following formula:
I PEAK = 40 A R OCSET - 0.4V R DSON (A)
Pulling and holding this pin below 0.15V with an open drain device, with very low parasitic capacitor, shuts down the IC with floating output and also resets the over-current counter. Releasing OCSET pin initiates a new soft-start and the converter works again. PHASE (Pin 8) The pin provides return path for the high-side MOSFET driver' pull-low current. Connect this pin to the highs side MOSFET' source. s
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APW7120A
Block Diagram
VCC
3VCC 40uA
Regulator Power-OnReset
OCSET
OC 0.4V 2.5V Enable Soft-Start and Fault Logic 0.15V
3VCC 67%VREF UV
POR
BOOT UGATE
Inhibit Gate Control
OV 118%VREF Soft-Start
PHASE
VCC
FB
Gm Amplifier
COMP PWM
VREF 0.8V
LGATE
FOSC 300kHz Oscillator
GND
Application Circuit
VBIAS
+5V/12V
C2 0.1F
2 8
D1 1N4148 C5 1F
L1 1uH
VIN
C3, C4 820F x2
+5/12V
BOOT
1
R4 2.2
5 VCC
UGATE PHASE
Q1 APM2512 L2 1.5uH Q2 APM2512
VOUT
C6, C7 1000F x2
C1 1F
6
U1 OCSET APW7120A
FB LGATE GND
7
R5
1.8V/15A
4
R1 1.5k
Shutdown
C3, C4 : 820F/16V , ESR=25 m C6, C7 : 1000F/6.3V, ESR=30 m
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3
Q3 2N7002
R2 1.2k C8 0.1F R3 200
APW7120A
Typical Operating Characteristics
Reference Voltage vs Junction Temperature
Switching Frequency vs Junction Temperature
0.812 0.810
350 340
Reference Voltage, VREF (V)
0.808 0.806 0.804 0.802 0.800 0.798 0.796 0.794 0.792 0.790 0.788 -50 -25 0 25 50 75 100 125 150
Switching Frequency, FOSC (kHz)
330 320 310 300 290 280 270 260 250 -50 -25 0 25 50 75 100 125 150
Junction Temperature (oC)
Junction Temperature (oC)
OCSET Current vs Junction Temperature
VCC POR Threshold Voltage vs Junction Temperature
45 44 43
4.4 4.3
VCC POR Threshold Voltage (V)
4.2 4.1 4.0 3.9 3.8 3.7 3.6 3.5 3.4
OCSET Current , IOCSET (A)
42 41 40 39 38 37 36 35 -50 -25 0 25 50 75 100 125 150
Rising VCC
Falling VCC
-50
-25
0
25
50
75
100
125
150
Junction Temperature (oC)
Junction Temperature (oC)
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APW7120A
Typical Operating Characteristics (Cont.)
OCSET Shutdown Threshold Voltage vs Junction Temperature
0.20
OCSET Shutdown Threshold Voltage (V)
Falling VOCSET
0.18
0.16
0.14
0.12
0.10 -50 -25 0 25 50 75 100 125 150
Junction Temperature (oC)
Operating Waveforms
(Refer to the typical application circuit, VBAIS=VIN=+12V supplied by an ATX Power Supply) 1. Load Transient Response : IOUT = 0A -> 15A -> 0A - IOUT slew rate = 7.5A/s
IOUT = 0A -> 15A IOUT = 0A -> 15A -> 0A
VOUT=1.8V VOUT
IOUT = 15A -> 0A
VOUT
1
VOUT VUGATE
1
VUGATE
1
VUGATE
3
IOUT
3
15A
3
IOUT
2
2
0A
IOUT
2
Ch1 : VOUT, 100mV/Div, AC, Ch2 : IOUT, 10A/Div Ch3 : VUGATE, 20V/Div, DC Time : 5s/Div BW = 20 MHz
Ch1 : VOUT, 100mV/Div, AC, Ch2 : IOUT, 10A/Div Ch3 : VUGATE, 20V/Div, DC Time : 40s/Div BW = 20 MHz
Ch1 : VOUT, 100mV/Div, AC, Ch2 : IOUT, 10A/Div Ch3 : VUGATE, 20V/Div, DC Time : 5s/Div BW = 20 MHz
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APW7120A
Operating Waveforms (Cont.)
(Refer to the typical application circuit, VBIAS=VIN=+12V supplied by an ATX Power Supply) 2. UGATE and LGATE Switching Waveforms
Rising VUGATE
IOUT = 15A
VLGATE VLGATE
Falling VUGATE
VUGATE
VUGATE
1,2
1,2
Ch1 : VUGATE, 5V/Div, DC Time : 20ns/Div
Ch2 : VLGATE, 2V/Div, DC BW = 500 MHz
Ch1 : VUGATE, 5V/Div, DC Ch2 : VLGATE, 2V/Div, DC Time : 20ns/Div BW = 500 MHz
3. Powering ON / OFF
Powering ON VCC=VIN=5V RL=0.12 Powering OFF VCC=VIN=5V RL=0.12
VCC
VCC
1
1
IL
IL
3
3
VOUT VOUT
2
2
Ch1 : VCC, 2V/Div, DC Ch3 : IL, 10A/Div, DC BW = 20 MHz
Ch2 : VOUT, 1V/Div, DC Time : 5ms/Div
Ch1 : VCC, 2V/Div, DC Ch3 : IL, 10A/Div, DC BW = 20 MHz 9
Ch2 : VOUT, 1V/Div, DC Time : 10ms/Div
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APW7120A
Operating Waveforms (Cont.)
(Refer to the typical application circuit, VBIAS=VIN=+12V supplied by an ATX Power Supply) 3. Powering ON / OFF (Cont.)
Powering ON VCC=VIN=12V RL=0.12 Powering OFF VCC=VIN=12V RL=0.12
VCC
1 1
VCC
IL IL
3
3
VOUT
VOUT
2
2
Ch1 : VCC, 5V/Div, DC Ch3 : IL, 10A/Div, DC BW = 20 MHz
Ch2 : VOUT, 1V/Div, DC Time : 5ms/Div
Ch1 : VCC, 5V/Div, DC Ch3 : IL, 10A/Div, DC BW = 20 MHz
Ch2 : VOUT, 1V/Div, DC Time : 10ms/Div
4. Enabling and Shutting Down
Enabling by Releasing OCSET Pin Shutting Down by Pulling OCSET Low
3
VOCSET
3
VOCSET
2
2
VUGATE
VUGATE
VOUT
1 1
VOUT
IOUT=2A
Ch1 : VOUT, 1V/Div, DC Ch2 : VUGATE, 20V/Div, DC Ch3 : VOCSET, 2V/Div, DC Time : 2ms/Div BW = 20 MHz Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Jun., 2008 10
Ch1 : VOUT, 1V/Div, DC Ch3 : VOCSET, 2V/Div, DC BW = 20 MHz
Ch2 : VUGATE, 20V/Div, DC Time : 2ms/Div
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APW7120A
Operating Waveforms (Cont.)
(Refer to the typical application circuit, VBIAS=VIN=+12V supplied by an ATX Power Supply) 5. Over-Current Protection
No Connecting a shutdown MOSFET at OCSET Pin
ROCSET=15k APM2512
Connecting a shutdown MOSFET (2N7002) at OCSET Pin
ROCSET=15k APM2512
1
VOUT
1
VOUT
2
IL
2
IL
Ch1 : VOUT, 1V/Div, DC Time : 5ms/Div
Ch2 : IL, 10A/Div, DC BW = 20 MHz
Ch1 : VOUT, 1V/Div, DC Time : 5ms/Div
Ch2 : IL, 10A/Div, DC BW = 20 MHz
6. OCSET Voltage RC Delay
No Connecting a shutdown MOSFET at OCSET Pin Connecting a shutdown MOSFET (2N7002) at OCSET Pin
VOCSET
VOCSET
IL
IL
1,2 CProber=8pF
OCP
1,2
CProber=8pF C2N7002=44pF (measured)
OCP
Ch1 : VOCSET, 0.5V/Div, DC Time : 2S/Div
Ch2 : IL, 10A/Div, DC BW = 20 MHz
Ch1 : VOCSET, 0.5V/Div, DC Time : 2 S/Div
Ch2 : IL, 10A/Div, DC BW = 20 MHz
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APW7120A
Operating Waveforms (Cont.)
(Refer to the typical application circuit, VBIAS=VIN=+12V supplied by an ATX Power Supply) 6. OCSET Voltage RC Delay (Cont.)
Connecting a shutdown MOSFET (APM2322) at OCSET Pin
7. Short-Circuit Test
Shorted by a wire
IL
1 UVP
OCP
OCP
OCP
OCP
VOUT
VOCSET
1,2
CProber=8pF CAPM2322=89pF (measured)
OCP
IL
2
Ch1 : VOCSET, 0.5V/Div, DC Ch2 : IL, 10A/Div, DC BW = 20 MHz Time : 2S/Div
Ch1 : VOUT, 1V/Div, DC Time : 5ms/Div
Ch2 : IL, 10A/Div, DC BW = 20 MHz
Function Description
Power-On-Reset (POR) The APW7120A monitors the VCC voltage (VCC) for Power-On-Reset function, preventing wrong logic operation during powering on. When the VCC voltage is ready, the APW7120A starts a start-up process and then ramps the output voltage up to the target voltage. Soft-Start The APW7120A has a built-in digital soft-start to control the output voltage rise and limit the current surge at the start-up. During soft-start, an internal ramp connected to the one of the positive inputs of the Gm amplifier rises up from 0V to 2V to replace the reference voltage (0.8V) until the ramp voltage reaches the reference
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voltage. The soft-start interval is about 3.2ms typical, independent of the converter' input and output s voltages. Over-Current Protection (OCP) The over-current function protects the switching c onver ter against over-current or short-circuit conditions. The controller senses the inductor current by detecting the drain-to-source voltage, product of the inductor' current and the on-resistance, of the s low-side MOSFET during it' on-state. This method s enhances the converter' efficiency and reduces cost s by eliminating a current sensing resistor. A resistor (ROCSET), connected from the OCSET to the
APW7120A
Function Description (Cont.)
Over-Current Protection (OCP) (Cont.) low-side MOSFET' drain, programs the over-current s trip level. An internal 40A (typical) current source flowing through the ROCSET develops a voltage (VROCSET) across the ROCSET. When the VOCSET (VROCSET+ VDS of the low-side MOSFET) is less than the internal overcurrent reference voltage (0.4V, typical), the IC shuts off the converter and then initiates a new soft-start process. After 4 over-current events are counted, the device turns off both high-side and low-side MOSFETs and the converter' output is latched to be floating. s Please pay attention to the RC delay effect. It causes the OCP trip level to be the function of the operating duty. The parasitic capacitance (including the capacitance inside the OCSET, external PCB trace capacitance and the COSS of the shutdown MOSFET) must be minimized, especially selecting a shutdown MOSFET with very small COSS. The OCP trip level follows the duty to increase a little at low operating duty, but very much at high operating duty, like the RC delay curve. Due to load regulation or current-limit, heavy load normally reduces converter' input voltage s and increases the power loses. During heavy load, the APW7120A regulates the output voltage by expending the duty. This rises up the OCP trip level at the same time. Under-Voltage Protection (UVP) The under-voltage function monitors the FB voltage (VFB) to protect the converter against short-circuit conditions. When the VFB falls below the falling UVP threshold (67% VREF), the APW7120A shuts off the converter. After a preceding delay, which starts at the beginning of the under-voltage shutdown, the APW 7120A initiates a new soft-start to resume regulating. The under-voltage protection shuts off and then re-starts the converter repeatedly without latching. The function is disabled during soft-start process. Over-Voltage Protection (OVP) The over-voltage protection monitors the FB voltage to prevent the output from over-voltage. When the output voltage rises to 118% of the nominal output voltage, the APW 7120A turns on the low-side MOSFET until the output voltage falls below the OVP threshold, regulating the output voltage around the OVP thresholds. Adaptive Shoot-Through Protection The gate driver incorporates adaptive shoot-through protection to high-side and low-side MOSFETs from conducting simultaneously and shorting the input supply. This is accomplished by ensuring the falling gate has turned off one MOSFET before the other is allowed to rise. During turn-off of the low-side MOSFET, the LGATE voltage is monitored until it reaches a 1.5V threshold, at which time the UGATE is released to rise after a constant delay. During turn-off of the high-side MOSFET, the UGATE-to-PHASE voltage is also monitored until it reaches a 1.5V threshold, at which time the LGATE is released to rise after a constant delay. Shutdown Control Pulling the OCSET voltage below 0.15V by an open drain transistor, shown in typical application circuit, shuts down the APW7120A PWM controller. In shutdown mode, the UGATE and LGATE are pulled to PHASE and GND respectively, the output is floating.
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APW7120A
Application Information
Input Capacitor Selection Use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the surge current needed each time high-side MOSFET(Q1) turns on. Place the small ceramic capacitors physically close to the MOSFETs and between the drain of Q1 and the source of low-side MOSFET(Q2). The important parameters for the bulk input capacitor are the voltage rating and the RMS current rating. For reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. The RMS current of the bulk input capacitor is calculated as the following equation : Output Capacitor Selection An output capacitor is required to filter the output and supply the load transient current. The filtering requirements are a function of the switching frequency and the ripple current. The output ripple is the sum of the voltages, having phase shift, across the ESR and the ideal output capacitor. The peak-to-peak voltage of the ESR is calculated as the following equations :
VOUT ICOUT
V OUT T=1/FOSC
VUGATE
DT
I IOUT
IL IOUT IQ1 I
Figure 1 Buck Converter Waveforms
IRMS = IOUT D (1 - D)
(A)
For a through hole design, several electrolytic capacitors may be needed. For surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating.
V IN IQ1
Q1
CIN
V OUT = D V IN V OUT (1 - D) I = F OSC L V ESR = I ESR
(V) .......... . (1) (A) .......... .(2) (V) .......... ..(3)
The peak-to-peak voltage of the ideal output capacitor
UGATE
IL
L
IOUT V OUT ESR COUT
is calculated as the following equation :
V COUT = I (V) ....... (4) 8 F OSC C OUT
LGATE
Q2
ICOUT
For general applications using bulk capacitors, the V COUT is much smaller than the VESR and can be ignored. Therefore, the AC peak-to-peak output voltage is shown below: V OUT = I ESR
(V) .......... .(5)
The load transient requirements are the function of
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APW7120A
Application Information (Cont.)
Output Capacitor Selection (Cont.) the slew rate (di/dt) and the magnitude of the transient load current. These requirements are generally met with a mix of capacitors and careful layout. Modern components and loads are capable of producing transient load rates above 1A/ns. High frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the ESR (Effective Series Resistance) and voltage rating requirements rather than actual capacitance requirements. High frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. An aluminum electrolytic capacitor' ESR value is res lated to the case size with lower ESR available in larger case sizes. However, the Equivalent Series Inductance (ESL) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. In most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor. Output Inductor Selection The output inductor is selected to meet the output voltage ripple requirements and minimize the converter' response time to the load transient. The s inductor value determines the converter' ripple s current and the ripple voltage, see equations (2) and (5). Increasing the value of inductance reduces the ripple current and voltage. However, the large inductance
values reduce the converter' response time to a load s
to a load transient is the time required to change the inductor current. Given a sufficiently fast control loop design, the APW7120A will provide either 0% or 85% (Average) duty cycle in response to a load transient. The response time is the time required to slew the inductor current from an initial current value to the transient current level. During this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor. Minimizing the response time can minimize the output capacitance required. The response time to a transient is different for the application of load and the removal of load. The following equations give the approximate response time interval for application and removal of a transient load:
L ITRAN L ITRAN , tFALL = V IN - V OUT V OUT where: ITRAN is the transient load current step, tRISE is the response time to the application of load, and tFALL is the response time to the removal of load. The worst case response time can be either at the application or removal of load. Be sure to check both of these equations at the transient load current. These requirements are minimum and maximum output levels for the worst case response time. tRISE =
MOSFET Selection The APW7120A requires two N-Channel power MOSFETs. These should be selected based upon R DS(ON) , gate supply requirements, and thermal management requirements. In high-current applications, the MOSFET power dissipation, package selection and heatsink are the dominant design factors. The power dissipation includes two loss components, conduction loss and switching loss. The conduction losses are the largest component of power dissipation for both the high-side and the
transient. One of the parameters limiting the converter' response s
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APW7120A
Application Information (Cont.)
MOSFET Selection (Cont.) low-side MOSFETs. These losses are distributed between the two MOSFETs according to duty factor (see the equations below). Only the high-side MOSFET has switching losses, since the low-side MOSFETs body diode or an external Schottky rectifier across the lower MOSFET clamps the switching node before the synchronous rectifier turns on. These equations assume linear voltage-current transitions and do not adequately model power loss due the reverse-recovery of the low-side MOSFET' body diode. The gates charge losses are dissipated by the APW7120A and don' heat the MOSFETs. However, large gate-charge t increases the switching interval, tSW which increases the high-side MOSFET switching losses. Ensure that both MOSFETs are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermalresistance specifications. A separate heatsink may be necessary depending upon MOSFET power, package type, ambient temperature and air flow.
A2(S) =
A3(S) = A1(S) =
VCOMP
FB Internal Compensation Network
VIN APW7120 VOSC=1.6V VPHASE Driver
LGATE
UGATE
L
VOUT R VO C
VFB
R1
R2
0.8V
Figure 2. APW7120 Control System The transfer functions are defined as following :
VFB(S) R2 = VO(S) R1 + R2
VCOMP(S) (Internal Compensation) VFB(S)
VPHASE(S) VIN = VCOMP(S) VOSC
1 PHigh - Side = IOUT RDSON D + IOUT VIN tSW FOSC 2 2 PLow - Side = IOUT RDSON (1 - D)
2
A4(S) =
ACL(S) =
VOUT(S) R CS +1 = VPHASE(S) L C S2 + R C S + 1
Where : tSW is the switching interval Feedback Compensation The figure 2 shows the control system of the APW7120, which consists of an internal voltage-mode PWM modulator, an output L-C filter, a resistor-divider and an internal compensation network. The R and C are the equivalent series resistance(ESR) and capacitance of the output capacitor; the L is the inductance of the output inductor.
VOUT (S) VO(S) VFB(S) VCOMP(S) VPHASE(S) VOUT(S) = VO(S) VFB(S) VCOMP(S) VPHASE(S) = A1(S) A2(S) A3(S) A4(S)
where A1(S) is the transfer function of the resistordivider, A2(S) is the transfer function of the feedback compensation network, A3(S) is the transfer function of the PWM modulator, A4(S) is the transfer function of the output LC filter, and ACL(S) is the transfer function of the closed-loop control system. Refer to figure 3. The Pole and Zero frequencies of the A1(S), A2(S), A3(S), and ACL(S) are shown or calculated as the following equations:
FZA21 = 0.4kHz (FZ) FPA21 = 430kHz (FP2)
FPA41,2 =
1 2 x LC
FZA41 =
1 2 xRxC
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Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Jun., 2008
16
APW7120A
Application Information (Cont.)
Feedback Compensation (Cont.) where the FPA21 (or FP2) and FZA21 (or Fz) are the Pole and Zero frequencies of the A2(S), the FPA41,2 and FZA41 are the double-Pole and Zero frequencies of the A4 (S), the VIN is the input voltage of the PWM converter and the load resistance of the converter is very large. For good converter stability, the values of the L, C, and R must be selected to meet the following criteria: 1.Make sure the double-pole frequency(FPA41,2) of the output filter is bigger than the zero frequency (FZA21) of the internal compensation network. 2. The following equation must be true:
log( VIN R2 1L ) + log( ) - 2 log( ) + 1.2 > 0 VOSC R1 + R2 RC
Layout Consideration In high power switching regulator, a correct layout is important to ensure proper operation of the regulator. In general, interconnecting impedances should be minimized by using short, wide printed circuit traces. Signal and power grounds are to be kept separate and finally combined using ground plane construction or single point grounding. Figure 4 illustrates the layout, with bold lines indicating high current paths. Components along the bold lines should be placed close together. Below is a checklist for your layout: 1. Begin the layout by placing the power components first. Orient the power circuitry to chieve a clean power flow path. If possible, make all the connections on one side of the PCB with wide, copper filled areas. 2. Connect the ground of feedback divider directly to the GND pin of the IC using a dedicated ground trace. 3. The VCC decoupling capacitor should be right next to the VCC and GND pins. Capacitor CBOOT should be connected as close to the BOOT and PHASE pins as possible. 4. Minimize the length and increase the width of the trace between UGATE/LGATE and the gates of the MOSFETs to reduce the impedance driving the MOSFETs. 5. Use an dedicated trace to connect the ROCSET and the Drain pad of the low-side MOSFET, Kevin connection , for accurate current sensing. 6. Keep the switching nodes (UGATE, LGATE, and
3. The converter crossover frequency (FCO) must be in the range of 10%~30% of minimum FOSC of the converter. The FCO is calculated by using the following equations:
Gain at FZA41 20 10% FOSC_MIN FCO = 10
FZA41 30% FOSC_MIN VIN R2 Gain at FZA41 = 20 log( ) + 20 log( ) VOSC R1 + R2
- 40 log(
1L ) + 27 RC
4. The values of L, C, and R selected must meet the equations above over the operaing temperature, voltage, and current ranges.
100 8 0 6 0 FZA21
Compensation Gain
Gain (dB)
4 0 2 0 0 -20 -40
PWM &Filter Gain
PHASE) away from sensitive small signal nodes
FPA21 F PA41,2 FC O FZA41
Converter Gain
since these nodes are fast moving signals. Therefore, keep traces to these nodes as short as possible. 7. Place the decoupling ceramic capacitor CHF near the Drain of the high-side MOSFET as close as possible. The bulk capacitors CIN are also placed near the Drain.
17 www.anpec.com.tw
-60 100
1 K
10K
100K
1M
10M
Frequency (f , Hz)
Figure 3. Converter Gain vs. Frequency
Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Jun., 2008
APW7120A
Application Information (Cont.)
Layout Consideration (Cont.) 8. Place the Source of the high-side MOSFET and the Drain of the low-side MOSFET as close as possible. Minimizing the impedance with wide layout plane between the two pads reduces the voltage bounce of the node. 9. Use a wide power ground plane, with low impedance, to connects the C HF , C IN , C OUT, Schottky diode and the Source of the low-side MOSFET to provide a low impedance path between the components for large and high frequency switching currents.
CHF
5 1 4
VIN
VCC BOOT LGATE APW7120A
CIN +
U 2 1UGATE
PHASE 8
Q1
Q2
+ L1
COUT
VOUT
Figure 4. Recommended Layout Digram
F
Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Jun., 2008
18
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APW7120A
Package Information
SOP-8
D SEE VIEW A
E1
E
e
b
h X 45
c
A2
0.25 GAUGE PLANE SEATING PLANE L VIEW A SOP-8 INCHES MIN. MAX.
S Y M B O L
MILLIMETERS MIN. MAX.
A A1 A2 b c D E E1 e h L 0
0.25 0.40 0 0.10 1.25 0.31 0.17 4.80 5.80 3.80 1.27 BSC
A1
A
1.75 0.25 0.004 0.049 0.51 0.25 5.00 6.20 4.00 0.012 0.007 0.189 0.228 0.150 0.050 BSC 0.50 1.27 8 0.010 0.016 0
0.069 0.010
0.020 0.010 0.197 0.244 0.157
0.020 0.050 8
Note: 1. Follow JEDEC MS-012 AA. 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side. 3. Dimension "E" does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side.
Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Jun., 2008 19 www.anpec.com.tw
APW7120A
Carrier Tape & Reel Dimensions
OD0 P0 P2 P1 A E1 F K0 B SECTION A-A T B0 A0 OD1 B A SECTION B-B
d
Application
A
H
H A
T1
T1
C
d
D
W
W
E1
F 5.5O .05 0 K0
330.0O .00 50 MIN. 2 SOP-8 P0 4.0O .10 0 P1 8.0O .10 0
12.4+2.00 13.0+0.50 1.5 MIN. -0.00 -0.20 P2 2.0O .05 0 D0 1.5+0.10 -0.00 D1 1.5 MIN.
20.2 MIN. 12.0O .30 1.75O .10 0 0 T A0 B0
0.6+0.00 6.40O .20 5.20O .20 2.10O .20 0 0 0 -0.40 (mm)
Devices Per Unit
Package Type SOP-8 Unit Tape & Reel Quantity 2500
Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Jun., 2008
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APW7120A
Reflow Condition
TP
(IR/Convection or VPR Reflow)
tp Critical Zone TL to TP Ramp-up
TL
Temperature
tL Tsmax
Tsmin Ramp-down ts Preheat
25
t 25C to Peak
Time
Reliability Test Program
Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B, A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Description 245C, 5 sec 1000 Hrs Bias @125C 168 Hrs, 100%RH, 121C -65C~150C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms, 1tr > 100mA
Classification Reflow Profiles
Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (TL) - Time (tL) Peak/Classification Temperature (Tp) Time within 5C of actual Peak Temperature (tp) Ramp-down Rate Time 25C to Peak Temperature Sn-Pb Eutectic Assembly 3C/second max. 100C 150C 60-120 seconds 183C 60-150 seconds See table 1 10-30 seconds 6C/second max. 6 minutes max. Pb-Free Assembly 3C/second max. 150C 200C 60-180 seconds 217C 60-150 seconds See table 2 20-40 seconds 6C/second max. 8 minutes max.
Note: All temperatures refer to topside of the package. Measured on the body surface.
Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Jun., 2008
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APW7120A
Classification Reflow Profiles (Cont.)
Table 1. SnPb Eutectic Process - Package Peak Reflow Temperatures Package Thickness <2.5 mm 2.5 mm Volume mm3 <350 240 +0/-5C 225 +0/-5C Volume mm3 350 225 +0/-5C 225 +0/-5C
Table 2. Pb-free Process - Package Classification Reflow Temperatures Package Thickness Volume mm <350
3
Volume mm 350-2000
3
Volume mm >2000
3
<1.6 mm 260 +0C* 260 +0C* 260 +0C* 1.6 mm - 2.5 mm 260 +0C* 250 +0C* 245 +0C* 2.5 mm 250 +0C* 245 +0C* 245 +0C* * Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0C. For example 260C+0C) at the rated MSL level.
Customer Service
Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838
Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Jun., 2008
22
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